DDR3/4 DRAM Memory Controller – Test

ddr3-4-controller-new2

SoC companies are faced with a challenge during the early stage of chip design to choose between DDR3 and DDR4, as
they are skeptic about their performance requirements. We, at Arastu, have developed a DDR3/4 DRAM Memory Single
Controller, which gives designers the flexibility to choose DRAM memories that fits best into their needs. The hardware for the controller is generated based on the parameters configured by the user. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. It is optimized for ASIC and FPGA designs.

Product Brief

LPDDR3/4 DRAM Memory Controller

LPDDR3-4-Controller

High-end computing applications requires Higher Performance keeping the Power and Latency intact. On customer demand, after successful implementation of LPDDR4 Memory Controller, Arastu Systems have developed a LPDDR3/4 DRAM Memory Controller in order to support wide range of application using the same design. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. The controller is optimized for ASIC and FPGA designs.

Product Brief

DRAM Controllers

dram-controller

Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power.

Memory controllers, which control the flow of data between CPU and memory, determine the response time of the requests made to memory and so play a critical role in assuring strong overall system performance.

A poorly designed memory controller can lead to inefficient use of the CPU memory interface, low utilization of the memory access bus, and large slowdowns in CPU performance in many applications. In contrast, a well-designed memory controller not only handles CPU memory requests efficiently, but can reorder them to exploit different degrees of parallelism available in modern DRAM systems, leading to a reduction in request latency and faster CPU performance. Furthermore, this improved sequence of memory accesses can lead to a reduction in energy used by the off-chip memory, which is often a significant fraction of overall system power.

Bearing in mind the market challenges, Arastu Systems offers,

DDR Memory Verification Components

ddr-vips

Memory Interface is a critical part of the SoC. The power and performance demands will continue to increase, driving continued advances and evolution of the memory interfaces at the front to provide an enhanced experience. The designer community is confronted with challenges of delivering on these demands as the consumer market, and the mobile segment, in particular, continue to evolve. The increased complexity of SoC’s has led to a need for more advanced verification techniques to minimize the development risks.

Arastu Systems offers a comprehensive Low Power Verification Suite which is fully compliant to respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA or SoC.

Arastu’s comprehensive Low Power Verification Suite includes,

Networking IPs

networking-ips

The rapid expansion of automated and algorithmic trading has increased the critical role of network and server technology in market trading. A delay of even one second in transmission time can result in million dollars losses for many time-critical applications.

Arastu System understands the market requirements and offers Ethernet solutions which cater the low latency & high throughput markets in order to process high volume of transaction.

Upcoming Products

upcoming-products

Arastu Systems have been proactively developing products in the area of Memory and its affiliated markets. We understand the challenge to meet the demands for more capacity, higher bandwidth & smarter utilization of memory for various applications.

Arastu Systems is also open to developing new products through collaborations. As business projects get larger, technology more expensive, and the costs of failure too large to be borne alone, businesses feel the need to work in joint developments. We, at Arastu, get encouraged to work with our partner to make them successful and fulfill our need. We know, the mutual benefits will lead to a successful partnership and product.

The company is well funded by a strong set of strategic and financial investors. Arastu is a team of proud and smart working Engineers led by visionary Industry Veterans.

We do share the detailed plan and roadmap under NDA. To know more, mail us at marcom@arastusystems.com.

(LP)DDR DFI PHY Functional Model

(LP)DDR DFI PHY Functional Model is fully compliant to respective DFI specifications and provides an effective and efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DRAM Memory Model and (LP)DDR DRAM Bus Monitor.

The DFI model is a digital model for DDR PHY. It is developed using SystemVerilog to facilitate seamless integration in any verification environment. Some of it features are as follows, ,

  • Supports all (LP)DDR control, command, data, update & error interface
  • Configurable date interface latency
  • Supports on-the-fly frequency change request
  • Support for all (LP)DDR training & related checkers
  • Clock disable support
  • Supports 1:1, 1:2 and 1:4 Memory Controller to PHY frequency ratio
  • Supports different topology in case of DIMM instantiation
  • Seamless integration with (LP)DDR Memory Controller

 
To learn more about the product, please reach us at marcom@arastusystems.com.

(LP)DDR DRAM Bus Monitor

lpddr4-bus-monitor

(LP)DDR DRAM Bus Monitor is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DRAM DFI Functional Model and (LP)DDR DRAM Memory Model.

The Bus Monitor is available in pure SystemVerilog which facilitates seamless integration in any verification environment. It provides per channel DRAM transaction tracker for faster debug. The Monitor runs in every major simulation environment. Moreover, it supports,

  • (LP)DDR memory devices from all leading vendors
  • Multiple device densities: 4Gb to 32Gb
  • Capturing of all the valid (LP)DDR commands as per the specifications
  • Reports DRAM bus utilization in different formats
  • On-the-fly protocol and data checking
  • In-built virtual memory support to detect data corruption from DRAM devices
  • Clock Stop and Dynamic frequency change to any valid DDR operating frequency
  • Provides guidance to Memory Controller to improve bus utilization (through Performance Predictor)

 
To learn more, please download the product brief or reach us at marcom@arastusystems.com.

(LP)DDR DRAM Memory Model

lpddr4-memory-model

(LP)DDR DRAM Memory Model is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DFI PHY Functional Model and (LP)DDR DRAM Bus Monitor.

The Memory Model is designed in SystemC/SystemVerilog to facilitate seamless integration in any verification environment. It provides per channel transaction tracker, thereby providing faster debug. It is readily available for usage to software developers. Additionally, it also supports,

  • Multiple device densities: 4Gb to 32Gb
  • Capturing of all the valid (LP)DDR commands as per the specifications
  • Programmable READ/WRITE latency and related timings
  • All Power Down modes
  • Data Bus Inversion (DBI) RD/WR and Data Mask (DM) WR
  • Multiple channels that can function independently
  • Reports all timing violations and protocol rule check

 
To learn more, please download the product brief or reach us at marcom@arastusystems.com.

DDR3 DRAM Memory Controller

ddr3-controller-new2

DDR3’s capability to bolster performance in system devices for a large number of applications have made it to be a widely accepted and established DRAM memory in the industry today. Considering the demand, we at Arastu, have developed a robust and flexible DDR3 DRAM Memory Controller IP and target to make the integration of DDR3 into your SoC a smooth one. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. The controller is fully optimized for ASIC and FPGA designs.

Product Brief