DDR3/4 DRAM Memory Controller

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SoC companies are faced with a challenge during the early stage of chip design to choose between DDR3 and DDR4, as they are skeptic about their performance requirements. Arastu’s DDR3/4 DRAM Memory Single Controller gives designers the flexibility to test and validate the system needs without compromising on cost and performance.

SoC companies are faced with a challenge during the early stage of chip design to choose between DDR3 and DDR4, as
they are skeptic about their performance requirements. We, at Arastu, have developed a DDR3/4 DRAM Memory Single
Controller, which gives designers the flexibility to choose DRAM memories that fits best into their needs. The hardware for the controller is generated based on the parameters configured by the user. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. It is optimized for ASIC and FPGA designs.

Product Brief

  • Fully compliant with JEDEC standard JESD79-3F & JESD79-4A for DDR3 and DDR4 respectively
  • Fully compliant with DFI3.1 PHY specifications
  • Compliant with JEDEC standard JEP175- (specific to DDR4)
  • Supports all DDR3/4 commands and trainings
  • BL8 and On-the-fly (BL8/BC4) programmable burst lengths
  • Multiple Power Down modes
  • Low Power Auto Self Refresh (LPASR) support
  • Supports upto eight ranks
  • Parameterized rank data widths 8, 16, 32, 64
  • Supports chip select interleaving
  • Registered Dual In-line Memory Module (RDIMM) and Load Reduced DIMM (LR-DIMM) support
  • Supports LCOM interface for NVDIMM
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio
  • Error Correction Code (ECC) Generation/Checking
  • Supports CRC computation across the data bus for error detection – (specific to DDR4)
  • Supports Parity generation for command/address bus to verify the integrity – (specific to DDR4)
  • Seamless error recovery in case of CRC/Parity error – (specific to DDR4)
  • Read Modify Write (RMW) – (Optional)
  • Row Hammering Detection (RHD) from data pattern – (Optional)
  • Software driver Post Package Repair and Target Row Refresh – (Optional)
  • Supports multiple host buses AMBA AXI4, AHB, Custom PIPE based Interface with parameterized address/data widths – (Optional)
  • Valuable add-on cores such as AHB/AXI, Multi-port Frontend and Reorder core available – (Optional)
  • Optimized for minimum ASIC gate count
  • Flexible licensing models
  • Customization and Integration services
  • Expert Technical support with maintenance updates
  • Computers and Gaming Consoles
  • Data Center and Server Market
  • Enterprise applications such as communication and networking
  • High-Performance Computing
  • Data Processing