Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power.
Memory controllers, which control the flow of data between CPU and memory, determine the response time of the requests made to memory and so play a critical role in assuring strong overall system performance.
A poorly designed memory controller can lead to inefficient use of the CPU memory interface, low utilization of the memory access bus, and large slowdowns in CPU performance in many applications. In contrast, a well-designed memory controller not only handles CPU memory requests efficiently, but can reorder them to exploit different degrees of parallelism available in modern DRAM systems, leading to a reduction in request latency and faster CPU performance. Furthermore, this improved sequence of memory accesses can lead to a reduction in energy used by the off-chip memory, which is often a significant fraction of overall system power.
Bearing in mind the market challenges, Arastu Systems offers,