(LP)DDR DFI PHY Functional Model

Fully compliant to respective DFI specifications and is developed using SystemC/SystemVerilog, so that it can be readily used by software developers.

(LP)DDR DFI PHY Functional Model is fully compliant to respective DFI specifications and provides an effective and efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DRAM Memory Model and (LP)DDR DRAM Bus Monitor.

The DFI model is a digital model for DDR PHY. It is developed using SystemVerilog to facilitate seamless integration in any verification environment. Some of it features are as follows, ,

  • Supports all (LP)DDR control, command, data, update & error interface
  • Configurable date interface latency
  • Supports on-the-fly frequency change request
  • Support for all (LP)DDR training & related checkers
  • Clock disable support
  • Supports 1:1, 1:2 and 1:4 Memory Controller to PHY frequency ratio
  • Supports different topology in case of DIMM instantiation
  • Seamless integration with (LP)DDR Memory Controller

 
To learn more about the product, please reach us at marcom@arastusystems.com.