(LP)DDR DRAM Bus Monitor is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DRAM DFI Functional Model and (LP)DDR DRAM Memory Model.
The Bus Monitor is available in pure SystemVerilog which facilitates seamless integration in any verification environment. It provides per channel DRAM transaction tracker for faster debug. The Monitor runs in every major simulation environment. Moreover, it supports,
- (LP)DDR memory devices from all leading vendors
- Multiple device densities: 4Gb to 32Gb
- Capturing of all the valid (LP)DDR commands as per the specifications
- Reports DRAM bus utilization in different formats
- On-the-fly protocol and data checking
- In-built virtual memory support to detect data corruption from DRAM devices
- Clock Stop and Dynamic frequency change to any valid DDR operating frequency
- Provides guidance to Memory Controller to improve bus utilization (through Performance Predictor)
To learn more, please download the product brief or reach us at firstname.lastname@example.org.