(LP)DDR DRAM Memory Model is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DFI PHY Functional Model and (LP)DDR DRAM Bus Monitor.
The Memory Model is designed in SystemC/SystemVerilog to facilitate seamless integration in any verification environment. It provides per channel transaction tracker, thereby providing faster debug. It is readily available for usage to software developers. Additionally, it also supports,
- Multiple device densities: 4Gb to 32Gb
- Capturing of all the valid (LP)DDR commands as per the specifications
- Programmable READ/WRITE latency and related timings
- All Power Down modes
- Data Bus Inversion (DBI) RD/WR and Data Mask (DM) WR
- Multiple channels that can function independently
- Reports all timing violations and protocol rule check
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