LPDDR3 DRAM Memory Controller

lpddr3-controller-new2
Fully compliant to JEDEC standard JESD209-3C. The Controller supports the popular industry standard AHB/AXI master, however, can be customized as per customer’s requirement.

Increased Bandwidth, Low Power Consumption, Extended Battery Life are some of the advantages the LPDDR3 DRAM offers in contrast to predecessors. At Arastu, we have developed a highly flexible and configurable design for LPDDR3 DRAM Memory Controller. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. The controller is optimized for ASIC and FPGA designs.

Product Brief

  • Fully compliant with JEDEC standard JESD209-3C and DFI3.1 PHY specifications
  • Supports all LPDDR3 commands and trainings
  • Parameterized LPDDR3 data-width (x16/x32) configuration
  • Self-Refresh, Auto Refresh and per bank refresh
  • Power Down and Deep Power Down modes
  • Support for In-line ECC
  • Facilitates device temperature changes using configurable ReadInterval to modify Refresh rate
  • System byte addressing (Mask Write) with uneven data strobe
  • Supports 1:1, 1:2 and 1:4 Memory Controller to PHY frequency ratio
  • Programmable to achieve Minimal Latency for a given applications
  • Maximizes DRAM bus utilization by implementing Look-Ahead command processing and Bank Management
  • Software driven runtime frequency change and power-down control
  • Plug-and-Play to customized PIPE interface
  • Valuable add-on cores such as AHB/AXI, TRR, APB testbus available – (Optional)
  • Supports upto 8 system host interfaces
  • Programmable Priority/QoS based system bus interface
  • Optimized for minimum ASIC gate count
  • Flexible licensing models
  • Customization and Integration services
  • Expert Technical support with maintenance updates
  • Extended battery life makes LPDDR3 to be a choice of memory for consumer devices such as
    Smartphone, Tablet, Ultrabook
  • Other Handheld mobile devices such as Gaming Consoles