(LP)DDR DRAM Bus Monitor

lpddr4-bus-monitor

(LP)DDR DRAM Bus Monitor is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DRAM DFI Functional Model and (LP)DDR DRAM Memory Model.

The Bus Monitor is available in pure SystemVerilog which facilitates seamless integration in any verification environment. It provides per channel DRAM transaction tracker for faster debug. The Monitor runs in every major simulation environment. Moreover, it supports,

  • (LP)DDR memory devices from all leading vendors
  • Multiple device densities: 4Gb to 32Gb
  • Capturing of all the valid (LP)DDR commands as per the specifications
  • Reports DRAM bus utilization in different formats
  • On-the-fly protocol and data checking
  • In-built virtual memory support to detect data corruption from DRAM devices
  • Clock Stop and Dynamic frequency change to any valid DDR operating frequency
  • Provides guidance to Memory Controller to improve bus utilization (through Performance Predictor)

 
To learn more, please download the product brief or reach us at marcom@arastusystems.com.

(LP)DDR DRAM Memory Model

lpddr4-memory-model

(LP)DDR DRAM Memory Model is implemented as per respective JEDEC standards and provides an effective & efficient way to verify the (LP)DDR components of an ASIC/FPGA system. It is a part of Arastu’s comprehensive low power verification suite which also includes (LP)DDR DFI PHY Functional Model and (LP)DDR DRAM Bus Monitor.

The Memory Model is designed in SystemC/SystemVerilog to facilitate seamless integration in any verification environment. It provides per channel transaction tracker, thereby providing faster debug. It is readily available for usage to software developers. Additionally, it also supports,

  • Multiple device densities: 4Gb to 32Gb
  • Capturing of all the valid (LP)DDR commands as per the specifications
  • Programmable READ/WRITE latency and related timings
  • All Power Down modes
  • Data Bus Inversion (DBI) RD/WR and Data Mask (DM) WR
  • Multiple channels that can function independently
  • Reports all timing violations and protocol rule check

 
To learn more, please download the product brief or reach us at marcom@arastusystems.com.

DDR3 DRAM Memory Controller

ddr3-controller-new2

DDR3’s capability to bolster performance in system devices for a large number of applications have made it to be a widely accepted and established DRAM memory in the industry today. Considering the demand, we at Arastu, have developed a robust and flexible DDR3 DRAM Memory Controller IP and target to make the integration of DDR3 into your SoC a smooth one. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. The controller is fully optimized for ASIC and FPGA designs.

Product Brief

LPDDR3 DRAM Memory Controller

lpddr3-controller-new2

Increased Bandwidth, Low Power Consumption, Extended Battery Life are some of the advantages the LPDDR3 DRAM offers in contrast to predecessors. At Arastu, we have developed a highly flexible and configurable design for LPDDR3 DRAM Memory Controller. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. The controller is optimized for ASIC and FPGA designs.

Product Brief

DDR4 DRAM Memory Controller

ddr4-controller-new2

DDR4 DRAM is no longer the memory only for Laptops and Servers, its ability to deliver increased performance and be highly reliable has led to its demand and adoption in multiple domains. At Arastu, we have developed a robust and flexible DDR4 DRAM Memory Controller IP and target to make the integration of DDR4 into your SoC a smooth one. The Design IP supports the popular industry standard AHB/AXI master, however, can be customized as per customer’s requirement. The controller is optimized for ASIC and FPGA designs.

Product Brief

DDR3/4 DRAM Memory Controller

ddr3-4-controller-new2

SoC companies are faced with a challenge during the early stage of chip design to choose between DDR3 and DDR4, as
they are skeptic about their performance requirements. We, at Arastu, have developed a DDR3/4 DRAM Memory Single
Controller, which gives designers the flexibility to choose DRAM memories that fits best into their needs. The hardware for the controller is generated based on the parameters configured by the user. The design IP supports the industry standard AHB/AXI, however, can be customized as per customer’s requirement. It is optimized for ASIC and FPGA designs.

Product Brief

LPDDR4 DRAM Memory Controller

lpddr4-controller-new2

LPDDR4 has taken the memory market by a storm owing to the advantages it offers. At Arastu, we target to make the integration of LPDDR4 into your SOCs a smooth one, with the help of our very robust and flexible LPDDR4 DRAM Memory Controller IP. The Design IP supports the popular industry standard AHB/AXI master, however, can be customized as per customer’s requirement. The core is compliant to JEDEC standard JESD209-4B.

Product Brief

Ethernet Network Switch IP Core

Arastu-Ethernet10G-Block-Diagram

Arastu System’s Ethernet 10G Switch IP Core is designed to fit into today’s FPGA and ASIC technologies with low gate count. The core can be easily configured to support multiple speed ports with fully non-blocking switching. The architecture is an optimized cut-through design which enables sub-100ns switch port-to-switch port latency.

Product Brief