Arastu Systems announces LPDDR3/4 Single Controller for optimal performance

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June 21st, 2017, San Jose, CA – High-end computing applications requires Higher Performance keeping the Power and Latency intact. Arastu Systems, a product engineering services company, today announced the immediate availability of LPDDR3/4 DRAM Memory Controller Core. The IP is highly configurable and delivers performance up to 4266 MT/s.

Dual DRAM Controller Core for LPDDR3 and LPDDR4 is as designed as per the respective JEDEC standards and is compatible with DFI3.1/4.0 PHY or a PHY from any vendor. It supports all key LPDDR3/4 features such as various frequency ratios, programmability to achieve minimum latency, multiple channels with a privilege to configure each channel independently, multiple power down modes, parameterized data widths and many more.

Upon successful implementation of LPDDR4 Controller, Arastu Systems developed LPDDR3/4 joint solution in order to meet customer needs. SoC designers who are planning to run the design at multiple speeds can leverage Arastu Systems’ LPDDR3/4 IP core and will have the benefit of supporting wide range of system application using the same design. The user can configure the IP core by parameter for LPDDR3/4, based on which the hardware for the controller is generated.

“We are gradually moving in an era where end user systems are becoming highly intelligent and performing complex functions seamlessly”, Umesh Patel, CEO, Arastu Systems. “Arastu’s team is playing a small but key role by empowering such systems with highly efficient LPDDR Memory Solutions”.

For more information regarding the Arastu Systems LPDDR3/4 DRAM Memory Controller please visit, https://www.design-reuse.com/sip/lpddr3-4-dram-memory-controller-ip-42683/, else send an email to, marcom@arastusystems.com .

Media Contact:
Harsh Parikh, Manager, Marketing
marcom@arastusystems.com
+1-408-223-2374

Arastu Systems Ethernet 10G Digital Switch IP Soft Core for Time-Critical Applications

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April 19th, 2017, San Jose, CA – Time critical applications, such as Trading Stock Exchange’s, Airport Terminals etc. require systems that deliver high throughput with low latency, as negligence even by a millisecond can prove catastrophic for business. Bearing in mind the Industry needs, Arastu Systems, a company that specializes in delivering customized IP solution in the Networking and Memory area, today announced Ethernet 10G Digital Switch IP soft core, which is proven and is readily available for usage.

The switch is highly configurable and can be easily customized as per the customer’s needs. The designed architecture for the IP is an optimized cut-through design which enables sub 100ns port to port latency. It easily fits into today’s ASIC and FPGA technologies with low gate count. The core can be configured to support 3 to 24 ports, where each port can act as 10M/100M/1G/2.5G/10G Ethernet with fully non-blocking switching. It also supports features such as software based Multi-cast grouping, VLAN, CAM/RAM based lookup and many more.

Additionally, the IP offers complete support for Layer 2 protocol based switching for Unmanaged Switch and Managed Switch, partial support for Layer 3 protocol and optional support for Precision time protocol (PTP) 1588. The core fits to the serve the needs of multiple industries such as Industrial, Automotive, Audio Video Broadcasting. It also meets the requirements to fulfill various IoT (Internet of Things) applications on demand. Applications that use the wireless backhaul technology can also rely on Arastu Systems Ethernet solution to replace Application specific standard product (ASSP’s).

“The challenge in time-critical applications is to make sure the Lag Time is bare minimum” says Umesh Patel, CEO and Founder Arastu Systems. “Our Ethernet switch is soft design which customer can customize to fit in their need to bring their product faster to market”.

For more information regarding the Ethernet switch please visit, https://www.design-reuse.com/sip/ethernet-10g-switch-ip-core-ip-38782/, else you can also send email at marcom@arastusystems.com

Media Contact:
Harsh Parikh
Manager, Marketing and Business Development
marcom@arastusystems.com
+1-408-223-2374

Arastu Systems announces highly flexible and compact DDR3/4 single controller

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August 4th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing IPs in the Memory and Networking area today announced the immediate availability of an optimized DDR3/4 DRAM Controller Core, which gives users the flexibility to choose DRAM memories that fits best into their needs.

Dual DRAM Controller is designed as per respective JEDEC standards and works seamlessly with DFI 3.1 compatible PHY. The core is developed using standard synthesizable RTL and supports all key DDR3/DDR4 features and additional features like Error Correction Code (ECC) generation/checking, multiple power modes to reduce power consumption, intelligent scheduler to improve memory throughput, CRC computation, Parity detection, various frequency ratios and performance up to 3200 MT/s. This makes it an optimum solution for applications which require a combination of higher performance, more bus bandwidth and high reliability.

Arastu’s DDR3/4 DRAM Controller Core is best suitable for system designers who are in the early stages of planning and are skeptic about performance requirements. The solution can also be used for multiple purposes, as the user has the privilege to configure the IP by parameter for DDR3/4, based on which the hardware of the controller is generated.

“Our customers are faced with a challenge during the initial phase of chip design to choose either DDR3 or DDR4, as it is imperative to meet a maximum performance threshold while keeping in mind the memory cost” said Umesh Patel, Founder and CEO, Arastu Systems. “Our IP solution makes it easy for them, as it gives the flexibility to test and validate the system need without compromising on the cost and performance”.

For more information, please reach us at, marcom@arastusystems.com.

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development
marcom@arastusystems.com
+1-408-223-2374

Arastu System’s LPDDR3 Controller Core for Extended Battery Life

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December 23rd, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing IPs in the Memory and Networking area today announced the immediate availability of their LPDDR3 DRAM Memory Controller along with LPDDR4, that is optimized for FPGA and ASIC designs. It is designed specifically to cater the industry demand for LPDDR memories, which delivers increased performance at very lower power consumption, in contrast to predecessors.

The controller is fully compliant with JEDEC standard JESD209-3C and partner’s DFI PHY or DFI 3.1 PHY from any other vendor. The IP core supports various power down modes including ‘Deep Power Down’ which makes it to be an optimum choice for devices such as Smartphones, Tablets, Ultrabook, where performance is driven by increase in battery life. The core also supports multiple channels with a privilege to configure and manage each channel independently and parameterized data width.

Moreover, Arastu Systems offers valuable add-on cores such as ARM compatible interfaces, TRR, Test/Debug bus etc. which can be leveraged by customers based on their needs. Handheld gadgets such as Gaming consoles also utilizes LPDDR3 memories, as faster response rate is necessary for enhanced performance. Arastu’s LPDDR3 Controller suffices their needs. Additionally, if required, the solution is also available in combo format with LPDDR3 and LPDDR4 Single Joint DRAM Controller, which gives customers the flexibility to utilize either DRAM memory.

“Fresh approach was needed to improve performance of each system by reducing latency and utilizing DRAM bus bandwidth without increasing power consumption” says Umesh Patel, Founder and CEO of Arastu Systems. “Our LPDDR solutions can assist our customers make an easy transition”.

To learn more about the product, please visit, http://www.arastusystems.com/products/lpddr3-dram-memory-controller/ or you can also reach us at, marcom@arastusystems.com.

Media Contact:
Harsh Parikh
Manager, Marketing & PR
marcom@arastusystems.com
+1-408-223-2374

Improving Performance and Verification of a System Through an Intelligent Testbench

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INTRODUCTION

The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs. Pre-silicon verification for first-pass success using current verification approaches is just not enough. A unique approach is needed that not only verifies the design faster but also achieves consistent results. Intelligent testbench with automation is the answer to today’s manual verification approach.

ASICs today demand high-bandwidth operations; which in turn demand high bandwidth on a system memory bus, like a DRAM interface bus. It is imperative that a comprehensive verification plan also includes verification for performance and power along with functional features. Having a large number of variables makes verification more complex. But this adds confidence in ASIC/SoC completeness for an end user’s application. In order to achieve high system performance in any ASIC/SoC, DRAM bus bandwidth utilization is equally important for that system.

High bandwidth on DRAM means less idle DRAM cycles. Manually finding coverage holes in the verification of a DRAM bus is a tedious process. This article proposes a unique verification component that helps find these holes in an intelligent manner, and it discusses potential solutions and advantages over other verification approaches. Additionally, it proposes another intelligent component which helps in simulating real-world fault/error cases without waiting for a chip to get fabricated and tested and also discusses achieving seamless portability across all memory sub-systems.

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Tech Overhaul: An Ode to Faster Memories

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If you want to know a person’s ‘true’ side, give him or her a ‘slow’ computing device! This might sound like a joke but most people assume a ‘demonic’ avatar when they aren’t able to view videos, emails or play games on their hand-held gadgets such as phones or tablets at the desired speed. You could find them clenching their fists (this includes me)…
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LPDDR4: Now and for Next Generation

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The demand for smarter, power efficient and wallet friendly gadgets is almost never ending! Countless applications offered by such high end gadgets have brought the world to the consumer’s finger tips, thus making this industry an ever booming one. In order to have life like displays, faster processing speeds, better power management, one needs to strive towards developing not just better processors but also better memories. In recent times, LPDDR3 ..
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Schedule Based Verification

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In these highly competent times, the need of the hour is to provide a step higher than just a functionally verified IP. A functionally verified IP is great to begin with, but clubbing it with features such as to maximize system performance and minimize the power utilization is an absolute necessity..
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Arastu Systems’ DFI 3.1 compatible and validated DDR4 Controller Core for increased system performance and reliability

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June 7th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing IPs in the Memory and Networking area today announced its DDR4 DRAM Memory Controller considering the need for higher performing, higher densities memories in applications pertaining to Data Center and Enterprise market. The IP is compliant to popular industry standards as well customized for specific customer’s needs.

The controller is designed as per JEDEC standard JESD79-4A and works seamlessly with our partner’s DFI PHY or DFI 3.1 compatible PHY from any other vendor. The design IP is developed using standard synthesizable RTL and supports data rates up to 3200 MT/s. Thereby, increasing the DRAM performance up to 50% over the predecessors. Additionally, it also supports multiple power saving modes that includes Low Power Auto Self Refresh (LPASR) which helps saving power close to 35% from previous versions.

The design IP supports features such as CRC computation across the data bus for error detection, parity generation for command/address bus to verify the integrity. It provides seamless error recovery which reduces the complexity of error recovery process in contrast to earlier DDR versions. It also supports Error Correction Code (ECC) which helps in correcting single bit error, and is imperative in applications such as spacecraft communication where reliability is a key factor.

”Technologies such as Cloud Computing, Virtualization and High-Performance Computing  requires high-capacity and highly-reliable memory subsystems” said Umesh Patel, CEO and Founder, Arastu Systems. “We are assisting our customers with our robust, self-contained and highly modular DDR4 and the upcoming DDR3/4 combo solution”.

For more information, please reach us at, marcom@arastusystems.com.

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development
marcom@arastusystems.com
+1-408-223-2374

Arastu Systems announces DFI 4.0 compatible and validated LPDDR4 DRAM Memory Controller

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April 7th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing products in the Memory and Networking area, today announced its LPDDR4 DRAM Memory Controller to cater the increasing demand for high performance and low power memories. The design IP supports popular industry standard AHB/AXI, but gives customers the flexibility to customize the design as per their needs.

The controller is designed as per the JEDEC standard JESD209-4A and works seamlessly with partner’s DFI PHY or DFI 4.0 compatible PHY from other vendors. The IP is developed using verilog and supports speeds up to 3200 MTps (MegaTransfers per second) for applications where faster response rates and  faster processors are mandatory, in order to achieve optimized end user experience.

The LPDDR4 IP solution also saves power by supporting multiple power saving modes such as Self Refresh Power Down, Deep Power Down, thereby extending the battery life of consumer gadgets. It supports multiple channels and gives privilege to the user to configure and manage each channel independently and also maximizes DRAM bus utilization using Look-Ahead command processing and Bank Management.

The LPDDR4 DRAM controller facilitates secure access to memory thereby assuring protected data transfer mainly for applications such as Advanced Driver Assistance Systems and Infotainment in the automotive industry, where security is the key concern. The core also supports DRAM testing, thereby increasing the system’s reliability.

“DRAM business has always been challenging, the memory requirement for each system is  different and to add to that faster computing solution demand faster and better memories” said Umesh Patel, Founder and CEO, Arastu Systems. “Our highly configurable and easily customizable DRAM solution amalgamated with our focused approach and clear vision is helping us cater the market needs.”

For more information on the IP solution, please visit,
http://www.arastusystems.com/products/lpddr4-dram-memory-controller/

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development
marcom@arastusystems.com
+1-408-223-2374

Additional Resources:
http://www.design-reuse.com/articles/39419/lpddr4-now-and-for-next-generation.html
http://www.design-reuse.com/articles/38870/tech-overhaul-an-ode-to-faster-memories.html
http://www.arastusystems.com/resources/arastu-systems-launches-a-comprehensive-low-power-verification-suite-for-the-lpddr4-memory/