June 7th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing IPs in the Memory and Networking area today announced its DDR4 DRAM Memory Controller considering the need for higher performing, higher densities memories in applications pertaining to Data Center and Enterprise market. The IP is compliant to popular industry standards as well customized for specific customer’s needs.
The controller is designed as per JEDEC standard JESD79-4A and works seamlessly with our partner’s DFI PHY or DFI 3.1 compatible PHY from any other vendor. The design IP is developed using standard synthesizable RTL and supports data rates up to 3200 MT/s. Thereby, increasing the DRAM performance up to 50% over the predecessors. Additionally, it also supports multiple power saving modes that includes Low Power Auto Self Refresh (LPASR) which helps saving power close to 35% from previous versions.
The design IP supports features such as CRC computation across the data bus for error detection, parity generation for command/address bus to verify the integrity. It provides seamless error recovery which reduces the complexity of error recovery process in contrast to earlier DDR versions. It also supports Error Correction Code (ECC) which helps in correcting single bit error, and is imperative in applications such as spacecraft communication where reliability is a key factor.
”Technologies such as Cloud Computing, Virtualization and High-Performance Computing requires high-capacity and highly-reliable memory subsystems” said Umesh Patel, CEO and Founder, Arastu Systems. “We are assisting our customers with our robust, self-contained and highly modular DDR4 and the upcoming DDR3/4 combo solution”.
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