February 18th, 2015, San Jose, CA – Arastu Systems, a company that specializes in developing products in the Memory and Networking area, today announced its comprehensive Low Power Verification Suite which is fully compliant to JEDEC standard JESD209-4A and provides an effective way to verify the LPDDR4 based ASIC and FPGA system.
Arastu’s Low Power Verification Suite includes,
- SystemC based LPDDR4 DRAM Memory Model that provides per channel transaction to facilitate faster debug and can be readily used by Software Developers
- SystemC based LPDDR4 DRAM DFI PHY Functional Model that is fully compliant to DFI4.0 specifications
- SystemVerilog based LPDDR4 DRAM Bus Monitor which checks DRAM Bus as per the JESD209-4A specifications and provides guidance to the Memory Controller to improve Bus Performance
The entire suite easily integrates in any verification environment and is compatible with all major EDA tools. It provides customers the control to check for standard and non-standard erroneous scenarios.
“Addressing the new DRAM Memory market requires fresh thinking, we are carving that path with a proactive approach,” said Umesh Patel, Founder & CEO of Arastu Systems. “With our flexible licensing models and customization services, we look forward to assist our customers with their System on Chip (SoC) designs.”
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