Schedule Based Verification


In these highly competent times, the need of the hour is to provide a step higher than just a functionally verified IP. A functionally verified IP is great to begin with, but clubbing it with features such as to maximize system performance and minimize the power utilization is an absolute necessity..
Read more

Arastu Systems’ DFI 3.1 compatible and validated DDR4 Controller Core for increased system performance and reliability


June 7th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing IPs in the Memory and Networking area today announced its DDR4 DRAM Memory Controller considering the need for higher performing, higher densities memories in applications pertaining to Data Center and Enterprise market. The IP is compliant to popular industry standards as well customized for specific customer’s needs.

The controller is designed as per JEDEC standard JESD79-4A and works seamlessly with our partner’s DFI PHY or DFI 3.1 compatible PHY from any other vendor. The design IP is developed using standard synthesizable RTL and supports data rates up to 3200 MT/s. Thereby, increasing the DRAM performance up to 50% over the predecessors. Additionally, it also supports multiple power saving modes that includes Low Power Auto Self Refresh (LPASR) which helps saving power close to 35% from previous versions.

The design IP supports features such as CRC computation across the data bus for error detection, parity generation for command/address bus to verify the integrity. It provides seamless error recovery which reduces the complexity of error recovery process in contrast to earlier DDR versions. It also supports Error Correction Code (ECC) which helps in correcting single bit error, and is imperative in applications such as spacecraft communication where reliability is a key factor.

”Technologies such as Cloud Computing, Virtualization and High-Performance Computing  requires high-capacity and highly-reliable memory subsystems” said Umesh Patel, CEO and Founder, Arastu Systems. “We are assisting our customers with our robust, self-contained and highly modular DDR4 and the upcoming DDR3/4 combo solution”.

For more information, please reach us at,

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development

Arastu Systems announces DFI 4.0 compatible and validated LPDDR4 DRAM Memory Controller


April 7th, 2016, San Jose, CA – Arastu Systems, a company that specializes in developing products in the Memory and Networking area, today announced its LPDDR4 DRAM Memory Controller to cater the increasing demand for high performance and low power memories. The design IP supports popular industry standard AHB/AXI, but gives customers the flexibility to customize the design as per their needs.

The controller is designed as per the JEDEC standard JESD209-4A and works seamlessly with partner’s DFI PHY or DFI 4.0 compatible PHY from other vendors. The IP is developed using verilog and supports speeds up to 3200 MTps (MegaTransfers per second) for applications where faster response rates and  faster processors are mandatory, in order to achieve optimized end user experience.

The LPDDR4 IP solution also saves power by supporting multiple power saving modes such as Self Refresh Power Down, Deep Power Down, thereby extending the battery life of consumer gadgets. It supports multiple channels and gives privilege to the user to configure and manage each channel independently and also maximizes DRAM bus utilization using Look-Ahead command processing and Bank Management.

The LPDDR4 DRAM controller facilitates secure access to memory thereby assuring protected data transfer mainly for applications such as Advanced Driver Assistance Systems and Infotainment in the automotive industry, where security is the key concern. The core also supports DRAM testing, thereby increasing the system’s reliability.

“DRAM business has always been challenging, the memory requirement for each system is  different and to add to that faster computing solution demand faster and better memories” said Umesh Patel, Founder and CEO, Arastu Systems. “Our highly configurable and easily customizable DRAM solution amalgamated with our focused approach and clear vision is helping us cater the market needs.”

For more information on the IP solution, please visit,

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development

Additional Resources:

ARASTU SYSTEMS launches a Comprehensive Low Power Verification Suite for the LPDDR4 Memory


February 18th, 2015, San Jose, CA – Arastu Systems, a company that specializes in developing products in the Memory and Networking area, today announced its comprehensive Low Power Verification Suite which is fully compliant to JEDEC standard JESD209-4A and provides an effective way to verify the LPDDR4 based ASIC and FPGA system.

Arastu’s Low Power Verification Suite includes,

  • SystemC based LPDDR4 DRAM Memory Model that provides per channel transaction to facilitate faster debug and can be readily used by Software Developers
  • SystemC based LPDDR4 DRAM DFI PHY Functional Model that is fully compliant to DFI4.0 specifications
  • SystemVerilog based LPDDR4 DRAM Bus Monitor which checks DRAM Bus as per the JESD209-4A specifications and provides guidance to the Memory Controller to improve Bus Performance

The entire suite easily integrates in any verification environment and is compatible with all major EDA tools. It provides customers the control to check for standard and non-standard erroneous scenarios.

“Addressing the new DRAM Memory market requires fresh thinking, we are carving that path with a proactive approach,” said Umesh Patel, Founder & CEO of Arastu Systems. “With our flexible licensing models and customization services, we look forward to assist our customers with their System on Chip (SoC) designs.”

In order to request for more information, reach us at

Media Contact:
Harsh Parikh
Manager, Marketing & Business Development